In general, data processors are designed to execute one or more instructions, the respective control fields of which are defined according to one or more formats. Most instructions have at least one control field for selecting among the several user-accessible resources, such as working registers, defined by the architecture of the data processor. Unless the architecture is memory-oriented, such as the Texas Instruments 9900 family of data processors, there are a limited number of such working registers. This limited amount of registers generally determines the number of bits in a register select control field sufficient to address all working registers. Thus, for example, in an architecture having only 16 working registers, 4 register select bits are sufficient to address all of the 16 working registers. Extending such an architecture to include additional working registers generally requires either a reformatting of the instructions to accommodate the additional register selection bits or some mechanism for remapping the existing register selection bits onto the extended register set. The first alternative of adding additional register selection bits is unattractive because the additional bits which must be dedicated to register selection reduce the number of available bits for specifying other control functions, such as operations, within the instruction format. In addition, any reformatting renders incompatible all pre-existing code whereby code compatibility between microprocessors in a family of processors may be lost. The second alternative has been attempted in several conventional data processors.
In the architecture of the Zilog Z80, an enhanced version of the Intel 8080, a selected subset of the working registers were duplicated, and an Exchange instruction was defined for swapping the register pairs/sets. In the Z80, at any time, one or the other set of registers, but not both, were accessible.
In the Sun Microsystems SPARC architecture, a very complicated set of 128 "overlapping" register windows was defined. The currently active portion of the window was specified in a 5-bit Current Window Pointer in the Processor Status Register. Except for certain overlapping/global portions, simultaneous access to registers in other windows was impossible.
In the Advanced Risk Machine (ARM) architecture, most 32-bit instructions include one or more 4-bit register select fields to select among the 16 general purpose registers. However, in the THUMB extension to the basic ARM architecture, the 16-bit instructions provide only 3-bit register select fields, thus restricting access to the lowest 8 of the 16 registers. To allow at least limited access to the upper 8 registers, special formats of the Add, Compare, Move, and Branch instructions have been provided, in which single-bit register select extension fields in the instruction are logically concatenated with the 3-bit register select fields to restore full 4-bit register addressing. Thus, THUMB represents a third possible compromise between register file size and instruction set robustness.
In contrast to such architectures, an attempt can be made at the time the architecture is initially defined to provide a set of working registers so large as to satisfy all reasonably anticipated applications. For example, the Advanced Micro Devices 29000 architecture defines 192 general purpose registers, of which 64 are considered global and 128 are local. For convenience, access protection was provided on a 16-register bank granularity. It should be noted, however, that, other than for purposes of access protection, all 192 of the general purpose registers comprised a single linearly addressed register file and require full 8-bit register select fields.
In view of these and other limitations in the architecture of prior art data processors, it is an object of the present invention to provide an architecture for a data processor having a register file logically partitioned into at least two register banks. The architecture including an improved method and apparatus for selecting a respective one of the banks for each register access. In particular, the present invention provides a register bank selection method and apparatus which is independent of the architecture's instruction formats.